This invention relates to a control circuit for semiconductor electronic devices which include at least one power transistor.
The invention specifically concerns a control circuit for electronic power devices monolithically integrated on a semiconductor substrate which has been doped by a first dopant type and on which a first epitaxial layer doped by the same dopant type as the substrate has been grown, an isolation well doped by a second type of dopant being formed therein for at least a first transistor of the control circuit.
The invention also relates to a semiconductor electronic device structure, in particular a field-effect transistor.
Further, the invention relates to a process for making the above control circuit and semiconductor device structure.
As is well known, at least one control circuit comprising low voltage operating transistors and at least one high voltage operating power transistor are integrated into many electronic devices.
An isolation structure is used for the control circuit, and its related transistors are integrated in a single well, known as the isolation well, such as the one shown at 3' in FIG. 1.
FIG. 1 shows schematically a semiconductor IC device which has been integrated monolithically in accordance with prior art methods and comprises a control circuit C' and a power transistor TP of the bipolar NPN HV type.
The IC device has a pair of isolation terminals ISO1 and ISO2.
For simplicity of description, the control circuit C' of FIG. 1 has been depicted as having two bipolar components only, namely a transistor T1 of the NPN LV type and a transistor T2 of the PNP LV type.
The control transistors T1 and T2 are accommodated in a single isolation well 3' formed within an epitaxial layer 2' of the N-type grown on a substrate 1' of the N+ type.
The isolation well 3' is virtually a necessity with semiconductor devices of this kind, but involves the appearance of certain parasitic transistors which impair the proper operation of the control circuit.
The formation of each of the control transistors T1 and T2 involves the presence, in the isolation well 3', of respective buried layers 4' and 4" having a dopant type which is the opposite from that of the well 3'. These buried layers 4' and 4" are responsible for the appearance of several parasitic transistors.
A pair of parasitic transistors P1' and P2' are associated with the first control transistor T1. In this respect, FIG. 2 shows, drawn to an enlarged scale, a portion of FIG. 1 where just the transistor T1 and the layer 4' are provided. An equivalent electric circuit of the structure of FIG. 2 is shown in FIG. 3.
During normal operation of the device, when the transistor T1 would be saturated, the base-emitter junction of the parasitic transistor P2' is forward biased and its collector, which is coincident with a contact ISO1 of the isolation well 3', is at a ground reference potential GND. Under these conditions, the transistor P2' will be in the active zone and will inject current into an isolation area 9' which is associated with the contact ISO1 through a resistance Rp being the intrinsic resistance of well 3'.
It is desirable that such a current be prevented from producing a potential difference across the resistance Rp capable of also turning on the other parasitic transistor P1'.
This occurrence may result from the presence of ramp voltages applied to the substrate 1', which can charge a parasitic capacitance Cp, present between the substrate 1' and the well 3', and produce a current flow which can turn on the parasitic transistor P1'.
Likewise, associated with the control transistor T2 is a further pair of parasitic transistors P3' and P4' which add to the parasitic transistor P1'. For convenience of illustration, FIG. 4A is an enlarged view of the structure of the transistor T2, while FIG. 4B shows an equivalent electric circuit of FIG. 4A.
The presence of the parasitic transistor P1' is less critical to the control transistor T2 than to the previous transistor T1 because the emitter of the transistor P1' is at a higher voltage than the ground voltage, and to turn on the transistor P1', its base-emitter junction must be brought up to an even higher value. The current which is forced to flow through the resistance Rp is, therefore, a larger one if compared to the control transistor T1.
In conclusion, in order to prevent the parasitic transistor P1' from conducting, the following would be necessary:
to minimize the resistance Rp present between the transistor P1' and the isolation well 3' contacts ISO1 and ISO2, normally connected to ground GND: PA1 to minimize the current gain of the first parasitic transistor P1'; and PA1 to decrease the gain of the other parasitic transistors P2', P3' and P4'.
A first known technical solution to meet such requirements consists of using an isolation well 3' obtained by epitaxial growth rather than implantation followed by dopant diffusion.
In such a manner, the base of the parasitic transistor P1' is more strongly doped, and this brings down the transistor gain.
While being advantageous in many respects, this first solution fails to fully remove the effects of the transistor P1' or of the other parasitic transistors P2', P3', P4' present.
A second solution provides for the use of an intermediate epitaxial layer to make the base of the parasitic transistor P1' broader and more strongly doped, as described in U.S. Pat. No. 4,889,822, for example.
While the provision of this intermediate layer further decreases the gain of the parasitic transistor P1', not even this solution can completely rule out the possibility of the parasitic transistor being turned on.
The technical problem underlying this invention is to provide a control circuit adapted for monolithic integration, with at least one driven power transistor, and having such structural and functional features as to afford a drastic reduction in the parasitic components that appear in previously known solutions in the art.
The solutive idea on which the invention stands is one of providing the control circuit with at least one N-channel MOS transistor placed in a well in direct contact with the isolation well.
Based on this solutive idea, the technical problem is solved by a control circuit for electronic power devices monolithically integrated on a semiconductor substrate (1) which has been doped by a first dopant type (N) and on which a first epitaxial layer (2) doped by the same dopant type (N) as the substrate (1) has been grown, an isolation well (3) doped by a second type (P) of dopant being formed therein for at least a first transistor (M1) of the control circuit, wherein the first transistor (M1) is a field-effect transistor and is formed within a first well (8) in direct contact with the isolation well (3).
The problem is also solved by a process for making a control circuit for electronic semiconductor devices monolithically integrated along with at least one power component, being of a type which comprises a first epitaxial layer growing step carried out using a first dopant type (N), a step of implantation of a second dopant type (P) to define a buried layer for an isolation well (3), and a second growing step of a second epitaxial layer (5), and comprising further implantation steps to first define said isolation well (3), enclosing at least a first well (8) in the second epitaxial layer (5), and subsequently define a second well (6) to accommodate at least one field-effect transistor (M1) and being housed within and in direct contact with said first well (8).